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The following applets demonstrate the N-type and P-type transistors used in CMOS technology, the basic CMOS inverter, NAND and NOR gates, and finally a AOI32 complex gate.
The first applet illustrates the function of both N-type and P-type MOS transistors.
Click on the source and gate contacts of the transistors to toggle the corresponding voltage levels and watch the resulting output value on the drain contacts. The applet uses colors to display the different voltages.
Note that the N-type transistor is conducting when its input is '1', while the P-type transistor is conducting when its input is '0'. The applet displays the channel of a conducting transistor as a rectangle filled with the color of its source voltage. The channel of a nonconducting transistor is shown as rectangle outline in black.
Voltage levels are shown in colors as above: a logical '1' corresponding to electrical level VCC is shown in red, a logical '0' (corresponding to 0V or GND) in blue.
Again, a floating wire (not connected to either VCC or GND) is shown in orange. Because of parasitic effects, the voltage level on such wire may reach some undefined voltage between VCC and GND after some time. A floating wire will cause problems, when its voltage is around VCC/2, because a gate voltage around VCC/2 on either N-type and P-type transistors implies that the transistor is conducting. The applet illustrates why this is a serious problem: When both transistors are conducting, there is a direct path from VCC to GND, and this implies a short-circuit condition (shown in light green), which dissipates much energy and may destroy the device.
Click anywhere in the applet to toggle the input voltage for the inverter from GND to VCC to Z (unknown) to GND.
If the input voltage is '1' (VCC) the P-type transistor on top is nonconducting, but the N-type transistor is conducting and provides a path from GND to the output Y. The output level therefore is '0'. On the other hand, if the input level is '0', the P-type transistor is conducting and provides a path from VCC to the output Y, so that the output level is '1', while the N-type transistor is blocked.
If the input is floating, both transistors may be conducting and a short-circuit condition is possible:
But there is a dynamic current dissipation in CMOS gates. The applet below illustrates this effect for the CMOS inverter. The gate of a MOS transistor forms a small capacitor. Typical values for the gate capacity are of order Cg = 10 fF. If the input of the inverter is connected to VCC at time t1, this capacitor is charged (Charge Q = Cg * VCC). If the input is connected to GND at time t2 it is discharged. The net effect of this is a very small current of I = dQ/dt = (Cg * VCC)/(t2-t1).
However, due to several reasons the total current drawn by a big CMOS chip, for example a microprocessor, can be quite large:
On the other hand, the quiescent current in typical static CMOS ICs is very small. For example, an 2K*8 bit CMOS SRAM dissipates only 1 uA when idle.
The next applet illustrates the current dissipation in the CMOS inverter. If the input voltage stays at '1' or '0', either the N-type or the P-type transistor in nonconducting, and there is no current through the inverter.
The power consumption of static CMOS logic is therefore directly proportional to switching frequency.
Usage of the applets: The applets are similar to the Inverter applet. Wires with logical '1' (VCC) are again shown in red, wires with logical '0' (GND) in blue. Unknown floating values are shown in orange color, a short-circuit is shown in green.
Only if both inputs A and B are '0' (corresponding to GND), there is a conducting path from VCC to the output (output level '1'). A input combination with A or B '1' blocks the path from VCC to the output, but opens a path from GND to the output (so that the output level is '0').
Watch the voltage level between the two P-type transistors. If both are nonconducting, the voltage level is unknown (floating). However, as that wire is not connected to any MOS-transistor gate, there is no problem:
Again, the wires connecting the N-type transistors may have floating voltage levels when the transistors are nonconducting. That is no problem, because these wires are not connected to any transistor gate.
NOR gates with three and more inputs are constructed correspondingly - all P-type transistors are connected in series and the N-type transistors are connected in parallel between GND and the output Y.
However, the series connection of transistors implies longer propagation delay (especially for P-type transistors) and a voltage drop across the transistors. Therefore, NAND gates for actual CMOS cell libraries are usually limited to 4-inputs (4 N-type transistors in series) and NOR gates to 3-inputs (3 P-type transistors in series).
NAND and NOR gates with more inputs are realized as a combination of simpler gates with up to 3 (4) inputs.
Typical example for complex gates found in almost all cell libraries
are combinations of AND-OR-INVERT and OR-AND-INVERT gates.
For example, the gate for the logic function Y = !((A ^ B) | (C ^ D ^ E)) - that is, the NOT of the OR of two ANDs - is typically called an AOI32 gate. This gate is shown in the next applet. It needs 10 transistors only (5 pairs of N-type and P-type transistors, one pair for each input).
To simplify the circuit schematic, the input wires are not drawn completely. Rather, all input wires are broken into two pieces, connected to the corresponding N-type and P-type transistors. For example, to toggle the input voltage for input A, you can click both near the N-type or the P-type transistor gate connected to input A.
Note that again the N-type and P-type paths in this gate are complementary. P-type transistors connected in series correspond to N-type transistors connected in parallel, and vice versa.
The generalization to other complex gates should be obvious. Again, gates with more than three transistors connected in series are not used. Most cell libraries contain gates from AOI21 and OAI21 up to aOI33 and OAI33. Try to construct one of these on paper and understand how it works!
Therefore, the use of single N-type or P-type transistors as switches is limited to circuits, where the voltage drop across the conducting transistors is not critical. A series connection of transistors used as switches is usually not possible in digital circuits.
But a combination of N-type and P-type transistors allows to realize efficient switches in CMOS technology. The circuit consists of one N-type and one P-type transistor connected in parallel and controlled by inverted gate voltages. This circuit, called a transmission gate (T-gate) is demonstrated in the following applet:
To better demonstrate the switching behaviour of the T-gate, the new voltage just selected by clicking 'wins' over a previously selected.
If the gate voltage of the N-type transistor is '0', the P-type transistors has a gate voltage of '1' and both transistors are nonconducting. On the other hand, if the gate voltage of the N-type transistor is '1' and the gate voltage of the P-type transistor is '0', both transistors are conducting. If the source voltage is near VCC, there is a voltage drop across the N-type transistor but (almost) no voltage drop across the P-type transistor. If the source voltage is near GND, the N-type transistor has (almost) no voltage drop. Because of the symmetry of standard MOS transistors, there is no reason to differantiate between source and drain in a T-gate. The contacts are therefore usually called 'L' (left) and 'R' (right).
The applets shows how a D-latch can be realized using only 8 transistors (2 inverters and 2 T-gates), if both the clock and the inverted clock signal are available - a savings of 50% of transistors and therefore chip-area. If the inverted clock is not available, an additional inverter is needed to provide the control signal for the two T-gates, still with a savings of 10 transistors versus 16.
To simplify the circuit schematic, the C and NC wires are not drawn completely. Rather, the corresponding T-gate gate inputs are labeled with C or NC. Note that the input T-gate (on the left) is controlled by C, while the feedback T-gate (on top) is controlled by NC.
The function of the T-gate D-latch is very easy to understand. If the C input is '1', the input T-gate is conducting, and the data input value is connected to the first inverter input, which generates !D. The second inverter generates !!D = D, that is, the output Q equals D (the latch is transparent).
If the C input is switched to '0', the first T-gate is blocked while the feedback T-gate (whose R contact is connected to Q, which still equals D) is opened. Therefore, the circuit feeds its Q signal back to the first inverter (!Q) and to the second inverter !!Q=Q. That is, the value of Q is stored until the C input becomes '1' again.